A 0.4-V, 90 ∼ 350-MHz PLL with an active loop-filter charge pump

Joung Wook Moon, Kwang Chun Choi, Woo Young Choi

Research output: Contribution to journalArticlepeer-review

54 Citations (Scopus)


A 0.4-V phase-locked loop (PLL) that has much improved power efficiency is realized in standard 65-nm CMOS. The PLL employs a novel ultralow-voltage charge pump that compensates current mismatch with an active loop filter and produces significantly reduced reference spurs. Its voltage-controlled oscillator (VCO) is designed with the body-bias technique and includes an automatic frequency calibration circuit that provides low VCO gain and wide tuning range. The PLL output frequency can be tuned from 90 to 350 MHz. At 350-MHz output, the PLL consumes 109 μW, which corresponds to the power efficiency of 0.31 mW/GHz.

Original languageEnglish
Article number6805603
Pages (from-to)319-323
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Issue number5
Publication statusPublished - 2014 May

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering


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