A 0.4-V, 500-MHz, ultra-low-power phase-locked loop for near-threshold voltage operation

Joung Wook Moon; Sung Geun Kim; Dae Hyun Kwon; Woo Young Choi

doi:10.1109/CICC.2014.6946100

A 0.4-V, 500-MHz, ultra-low-power phase-locked loop for near-threshold voltage operation

Joung Wook Moon, Sung Geun Kim, Dae Hyun Kwon, Woo Young Choi

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

11 Citations (Scopus)

Abstract

We present a 500-MHz, ultra-low-power phase-locked loop (PLL) realized with the near-threshold supply voltage of 0.4 V in 65-nm CMOS technology. Our PLL employs a new charge pump (CP) circuit structure that can greatly reduce CP up/down current mismatch and their variation with voltage-controlled oscillator (VCO) control voltages. The PLL consumes only 127.8 μW, which corresponds to power efficiency of 0.256 mW/GHz.

Original language	English
Title of host publication	Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781479932863
DOIs	https://doi.org/10.1109/CICC.2014.6946100
Publication status	Published - 2014 Nov 4
Event	36th Annual Custom Integrated Circuits Conference - The Showcase for Integrated Circuit Design in the Heart of Silicon Valley, CICC 2014 - San Jose, United States Duration: 2014 Sept 15 → 2014 Sept 17

Publication series

Name	Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014

Other

Other	36th Annual Custom Integrated Circuits Conference - The Showcase for Integrated Circuit Design in the Heart of Silicon Valley, CICC 2014
Country/Territory	United States
City	San Jose
Period	14/9/15 → 14/9/17

Bibliographical note

Publisher Copyright:
© 2014 IEEE.

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Access to Document

10.1109/CICC.2014.6946100

Cite this

Moon, J. W., Kim, S. G., Kwon, D. H., & Choi, W. Y. (2014). A 0.4-V, 500-MHz, ultra-low-power phase-locked loop for near-threshold voltage operation. In Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014 [6946100] (Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CICC.2014.6946100

Moon, Joung Wook ; Kim, Sung Geun ; Kwon, Dae Hyun et al. / A 0.4-V, 500-MHz, ultra-low-power phase-locked loop for near-threshold voltage operation. Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014. Institute of Electrical and Electronics Engineers Inc., 2014. (Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014).

@inproceedings{cae9831138ef414b8a1523b20a2ebe24,

title = "A 0.4-V, 500-MHz, ultra-low-power phase-locked loop for near-threshold voltage operation",

abstract = "We present a 500-MHz, ultra-low-power phase-locked loop (PLL) realized with the near-threshold supply voltage of 0.4 V in 65-nm CMOS technology. Our PLL employs a new charge pump (CP) circuit structure that can greatly reduce CP up/down current mismatch and their variation with voltage-controlled oscillator (VCO) control voltages. The PLL consumes only 127.8 μW, which corresponds to power efficiency of 0.256 mW/GHz.",

author = "Moon, {Joung Wook} and Kim, {Sung Geun} and Kwon, {Dae Hyun} and Choi, {Woo Young}",

note = "Publisher Copyright: {\textcopyright} 2014 IEEE.; 36th Annual Custom Integrated Circuits Conference - The Showcase for Integrated Circuit Design in the Heart of Silicon Valley, CICC 2014 ; Conference date: 15-09-2014 Through 17-09-2014",

year = "2014",

month = nov,

day = "4",

doi = "10.1109/CICC.2014.6946100",

language = "English",

series = "Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014",

address = "United States",

}

Moon, JW, Kim, SG, Kwon, DH & Choi, WY 2014, A 0.4-V, 500-MHz, ultra-low-power phase-locked loop for near-threshold voltage operation. in Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014., 6946100, Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014, Institute of Electrical and Electronics Engineers Inc., 36th Annual Custom Integrated Circuits Conference - The Showcase for Integrated Circuit Design in the Heart of Silicon Valley, CICC 2014, San Jose, United States, 14/9/15. https://doi.org/10.1109/CICC.2014.6946100

A 0.4-V, 500-MHz, ultra-low-power phase-locked loop for near-threshold voltage operation. / Moon, Joung Wook; Kim, Sung Geun; Kwon, Dae Hyun et al.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014. Institute of Electrical and Electronics Engineers Inc., 2014. 6946100 (Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - A 0.4-V, 500-MHz, ultra-low-power phase-locked loop for near-threshold voltage operation

AU - Moon, Joung Wook

AU - Kim, Sung Geun

AU - Kwon, Dae Hyun

AU - Choi, Woo Young

PY - 2014/11/4

Y1 - 2014/11/4

N2 - We present a 500-MHz, ultra-low-power phase-locked loop (PLL) realized with the near-threshold supply voltage of 0.4 V in 65-nm CMOS technology. Our PLL employs a new charge pump (CP) circuit structure that can greatly reduce CP up/down current mismatch and their variation with voltage-controlled oscillator (VCO) control voltages. The PLL consumes only 127.8 μW, which corresponds to power efficiency of 0.256 mW/GHz.

AB - We present a 500-MHz, ultra-low-power phase-locked loop (PLL) realized with the near-threshold supply voltage of 0.4 V in 65-nm CMOS technology. Our PLL employs a new charge pump (CP) circuit structure that can greatly reduce CP up/down current mismatch and their variation with voltage-controlled oscillator (VCO) control voltages. The PLL consumes only 127.8 μW, which corresponds to power efficiency of 0.256 mW/GHz.

UR - http://www.scopus.com/inward/record.url?scp=84928152160&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84928152160&partnerID=8YFLogxK

U2 - 10.1109/CICC.2014.6946100

DO - 10.1109/CICC.2014.6946100

M3 - Conference contribution

AN - SCOPUS:84928152160

T3 - Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014

BT - Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 36th Annual Custom Integrated Circuits Conference - The Showcase for Integrated Circuit Design in the Heart of Silicon Valley, CICC 2014

Y2 - 15 September 2014 through 17 September 2014

ER -

Moon JW, Kim SG, Kwon DH, Choi WY. A 0.4-V, 500-MHz, ultra-low-power phase-locked loop for near-threshold voltage operation. In Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014. Institute of Electrical and Electronics Engineers Inc. 2014. 6946100. (Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014). doi: 10.1109/CICC.2014.6946100

A 0.4-V, 500-MHz, ultra-low-power phase-locked loop for near-threshold voltage operation

Abstract

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