A 0.36 pJ/bit, 12.5 Gb/s forwarded-clock receiver with a sample swapping scheme and a half-bit delay line

Woorham Bae; Gyu Seob Jeong; Kwanseo Park; Sung Yong Cho; Yoonsoo Kim; Deog Kyoon Jeong

doi:10.1109/ESSCIRC.2014.6942118

A 0.36 pJ/bit, 12.5 Gb/s forwarded-clock receiver with a sample swapping scheme and a half-bit delay line

Woorham Bae, Gyu Seob Jeong, Kwanseo Park, Sung Yong Cho, Yoonsoo Kim, Deog Kyoon Jeong

School of System & Semiconductor Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

5 Citations (Scopus)

Abstract

A 12.5Gb/s forwarded clock receiver based on a DLL with a bang-bang PD is presented. The stuck locking is detected and averted by swapping edge and data samples at the output of the PD. Moreover, required delay range of the VCDL is reduced by half with the proposed sample swapping scheme. The prototype chip exhibits the power efficiency of 0.36pJ/bit and occupies 0.025mm². Due to the wide jitter tracking bandwidth of DLL and the inherent jitter correlation between data and forwarded clock, the proposed receiver exhibits outstanding jitter tolerance whose corner frequency is higher than 300 MHz.

Original language	English
Title of host publication	ESSCIRC 2014 - Proceedings of the 40th European Solid-State Circuit Conference
Editors	Pietro Andreani, Andrea Bevilacqua, Gaudenzio Meneghesso
Publisher	IEEE Computer Society
Pages	447-450
Number of pages	4
ISBN (Electronic)	9781479956944
DOIs	https://doi.org/10.1109/ESSCIRC.2014.6942118
Publication status	Published - 2014 Oct 31
Event	40th European Solid-State Circuit Conference, ESSCIRC 2014 - Venezia Lido, Italy Duration: 2014 Sept 22 → 2014 Sept 26

Publication series

Name	European Solid-State Circuits Conference
ISSN (Print)	1930-8833

Conference

Conference	40th European Solid-State Circuit Conference, ESSCIRC 2014
Country/Territory	Italy
City	Venezia Lido
Period	14/9/22 → 14/9/26

Bibliographical note

Publisher Copyright:
© 2014 IEEE.

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ESSCIRC.2014.6942118

Cite this

Bae, W., Jeong, G. S., Park, K., Cho, S. Y., Kim, Y., & Jeong, D. K. (2014). A 0.36 pJ/bit, 12.5 Gb/s forwarded-clock receiver with a sample swapping scheme and a half-bit delay line. In P. Andreani, A. Bevilacqua, & G. Meneghesso (Eds.), ESSCIRC 2014 - Proceedings of the 40th European Solid-State Circuit Conference (pp. 447-450). Article 6942118 (European Solid-State Circuits Conference). IEEE Computer Society. https://doi.org/10.1109/ESSCIRC.2014.6942118

Bae, Woorham ; Jeong, Gyu Seob ; Park, Kwanseo et al. / A 0.36 pJ/bit, 12.5 Gb/s forwarded-clock receiver with a sample swapping scheme and a half-bit delay line. ESSCIRC 2014 - Proceedings of the 40th European Solid-State Circuit Conference. editor / Pietro Andreani ; Andrea Bevilacqua ; Gaudenzio Meneghesso. IEEE Computer Society, 2014. pp. 447-450 (European Solid-State Circuits Conference).

@inproceedings{9e34d209c57b4471b13b4bc62cea7c81,

title = "A 0.36 pJ/bit, 12.5 Gb/s forwarded-clock receiver with a sample swapping scheme and a half-bit delay line",

abstract = "A 12.5Gb/s forwarded clock receiver based on a DLL with a bang-bang PD is presented. The stuck locking is detected and averted by swapping edge and data samples at the output of the PD. Moreover, required delay range of the VCDL is reduced by half with the proposed sample swapping scheme. The prototype chip exhibits the power efficiency of 0.36pJ/bit and occupies 0.025mm2. Due to the wide jitter tracking bandwidth of DLL and the inherent jitter correlation between data and forwarded clock, the proposed receiver exhibits outstanding jitter tolerance whose corner frequency is higher than 300 MHz.",

author = "Woorham Bae and Jeong, {Gyu Seob} and Kwanseo Park and Cho, {Sung Yong} and Yoonsoo Kim and Jeong, {Deog Kyoon}",

note = "Publisher Copyright: {\textcopyright} 2014 IEEE.; 40th European Solid-State Circuit Conference, ESSCIRC 2014 ; Conference date: 22-09-2014 Through 26-09-2014",

year = "2014",

month = oct,

day = "31",

doi = "10.1109/ESSCIRC.2014.6942118",

language = "English",

series = "European Solid-State Circuits Conference",

publisher = "IEEE Computer Society",

pages = "447--450",

editor = "Pietro Andreani and Andrea Bevilacqua and Gaudenzio Meneghesso",

booktitle = "ESSCIRC 2014 - Proceedings of the 40th European Solid-State Circuit Conference",

address = "United States",

}

Bae, W, Jeong, GS, Park, K, Cho, SY, Kim, Y & Jeong, DK 2014, A 0.36 pJ/bit, 12.5 Gb/s forwarded-clock receiver with a sample swapping scheme and a half-bit delay line. in P Andreani, A Bevilacqua & G Meneghesso (eds), ESSCIRC 2014 - Proceedings of the 40th European Solid-State Circuit Conference., 6942118, European Solid-State Circuits Conference, IEEE Computer Society, pp. 447-450, 40th European Solid-State Circuit Conference, ESSCIRC 2014, Venezia Lido, Italy, 14/9/22. https://doi.org/10.1109/ESSCIRC.2014.6942118

A 0.36 pJ/bit, 12.5 Gb/s forwarded-clock receiver with a sample swapping scheme and a half-bit delay line. / Bae, Woorham; Jeong, Gyu Seob; Park, Kwanseo et al.
ESSCIRC 2014 - Proceedings of the 40th European Solid-State Circuit Conference. ed. / Pietro Andreani; Andrea Bevilacqua; Gaudenzio Meneghesso. IEEE Computer Society, 2014. p. 447-450 6942118 (European Solid-State Circuits Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - A 0.36 pJ/bit, 12.5 Gb/s forwarded-clock receiver with a sample swapping scheme and a half-bit delay line

AU - Bae, Woorham

AU - Jeong, Gyu Seob

AU - Park, Kwanseo

AU - Cho, Sung Yong

AU - Kim, Yoonsoo

AU - Jeong, Deog Kyoon

PY - 2014/10/31

Y1 - 2014/10/31

N2 - A 12.5Gb/s forwarded clock receiver based on a DLL with a bang-bang PD is presented. The stuck locking is detected and averted by swapping edge and data samples at the output of the PD. Moreover, required delay range of the VCDL is reduced by half with the proposed sample swapping scheme. The prototype chip exhibits the power efficiency of 0.36pJ/bit and occupies 0.025mm2. Due to the wide jitter tracking bandwidth of DLL and the inherent jitter correlation between data and forwarded clock, the proposed receiver exhibits outstanding jitter tolerance whose corner frequency is higher than 300 MHz.

AB - A 12.5Gb/s forwarded clock receiver based on a DLL with a bang-bang PD is presented. The stuck locking is detected and averted by swapping edge and data samples at the output of the PD. Moreover, required delay range of the VCDL is reduced by half with the proposed sample swapping scheme. The prototype chip exhibits the power efficiency of 0.36pJ/bit and occupies 0.025mm2. Due to the wide jitter tracking bandwidth of DLL and the inherent jitter correlation between data and forwarded clock, the proposed receiver exhibits outstanding jitter tolerance whose corner frequency is higher than 300 MHz.

UR - http://www.scopus.com/inward/record.url?scp=84909952253&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84909952253&partnerID=8YFLogxK

U2 - 10.1109/ESSCIRC.2014.6942118

DO - 10.1109/ESSCIRC.2014.6942118

M3 - Conference contribution

AN - SCOPUS:84909952253

T3 - European Solid-State Circuits Conference

SP - 447

EP - 450

BT - ESSCIRC 2014 - Proceedings of the 40th European Solid-State Circuit Conference

A2 - Andreani, Pietro

A2 - Bevilacqua, Andrea

A2 - Meneghesso, Gaudenzio

PB - IEEE Computer Society

T2 - 40th European Solid-State Circuit Conference, ESSCIRC 2014

Y2 - 22 September 2014 through 26 September 2014

ER -

Bae W, Jeong GS, Park K, Cho SY, Kim Y, Jeong DK. A 0.36 pJ/bit, 12.5 Gb/s forwarded-clock receiver with a sample swapping scheme and a half-bit delay line. In Andreani P, Bevilacqua A, Meneghesso G, editors, ESSCIRC 2014 - Proceedings of the 40th European Solid-State Circuit Conference. IEEE Computer Society. 2014. p. 447-450. 6942118. (European Solid-State Circuits Conference). doi: 10.1109/ESSCIRC.2014.6942118

A 0.36 pJ/bit, 12.5 Gb/s forwarded-clock receiver with a sample swapping scheme and a half-bit delay line

Abstract

Publication series

Conference

Bibliographical note

All Science Journal Classification (ASJC) codes

Access to Document

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