A 12.5Gb/s forwarded clock receiver based on a DLL with a bang-bang PD is presented. The stuck locking is detected and averted by swapping edge and data samples at the output of the PD. Moreover, required delay range of the VCDL is reduced by half with the proposed sample swapping scheme. The prototype chip exhibits the power efficiency of 0.36pJ/bit and occupies 0.025mm2. Due to the wide jitter tracking bandwidth of DLL and the inherent jitter correlation between data and forwarded clock, the proposed receiver exhibits outstanding jitter tolerance whose corner frequency is higher than 300 MHz.
|Title of host publication||ESSCIRC 2014 - Proceedings of the 40th European Solid-State Circuit Conference|
|Editors||Pietro Andreani, Andrea Bevilacqua, Gaudenzio Meneghesso|
|Publisher||IEEE Computer Society|
|Number of pages||4|
|Publication status||Published - 2014 Oct 31|
|Event||40th European Solid-State Circuit Conference, ESSCIRC 2014 - Venezia Lido, Italy|
Duration: 2014 Sept 22 → 2014 Sept 26
|Name||European Solid-State Circuits Conference|
|Conference||40th European Solid-State Circuit Conference, ESSCIRC 2014|
|Period||14/9/22 → 14/9/26|
Bibliographical notePublisher Copyright:
© 2014 IEEE.
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering