This paper presents a 65nm CMOS 1.62-to-l0.8Gb/s video interface receiver with fully adaptive equalizers incorporating CTLE and 2-tap DFE. Sign -sign least-mean-squares (SSLMS) algorithm is used for not only the DFE but also the CTLE adaptation to reduce power consumption and extra hardware. An un-even data level is proposed for the optimum locking of the adaptation in the presence of a pre cursor. The receiver achieves BER of 10-12 at 34dB loss channel, occupies 0.174 mm2, and consumes 37.2mW at 10.8Gb/s.
|Title of host publication||2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Publication status||Published - 2019 Jun|
|Event||33rd Symposium on VLSI Circuits, VLSI Circuits 2019 - Kyoto, Japan|
Duration: 2019 Jun 9 → 2019 Jun 14
|Name||IEEE Symposium on VLSI Circuits, Digest of Technical Papers|
|Conference||33rd Symposium on VLSI Circuits, VLSI Circuits 2019|
|Period||19/6/9 → 19/6/14|
Bibliographical notePublisher Copyright:
© 2019 JSAP.
All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering