A 0.166 pJ/b/pF, 3.5-5 Gb/s TSV I/O Interface with VOHDrift Control

Ji Young Kim; Jongsoo Lee; Kiryong Kim; Byoung Mo Moon; Seong Ook Jung

doi:10.1109/TCSII.2020.3039911

A 0.166 pJ/b/pF, 3.5-5 Gb/s TSV I/O Interface with V_OHDrift Control

Ji Young Kim, Jongsoo Lee, Kiryong Kim, Byoung Mo Moon, Seong Ook Jung

Department of Electrical and Electronic Engineering

Research output: Contribution to journal › Article › peer-review

5 Citations (Scopus)

Abstract

A voltage-mode transmitter (TX) with a predriver and a receiver (RX) with an energy-efficient level shifter (LS) is proposed to reduce power consumption in the heavy load of a through-silicon via (TSV) input-output (I/O) interface. An N-over-N (NN) driver with the proposed predriver reduces VOH drift to enhance jitter characteristics. In addition, the swing level of the transmitted signal can be lowered to 600 mV with a single supply voltage at the TX. To recover the swing level, the RX is designed with the proposed LS that can operate with a data rate of 5 Gb/s. An 8-stacked TSV is emulated in the 65 nm CMOS process, and the emulated capacitance of each stack is 100 fF. The energy efficiency is 0.166 pJ/b/pF with a pseudorandom binary sequence (PRBS)-7 at 5 Gb/s and 0.205 pJ/b/pF with a PRBS-31 at 3.5 Gb/s.

Original language	English
Article number	9268074
Pages (from-to)	1822-1826
Number of pages	5
Journal	IEEE Transactions on Circuits and Systems II: Express Briefs
Volume	68
Issue number	6
DOIs	https://doi.org/10.1109/TCSII.2020.3039911
Publication status	Published - 2021 Jun

Bibliographical note

Publisher Copyright:
© 2004-2012 IEEE.

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Access to Document

10.1109/TCSII.2020.3039911

Cite this

@article{d6faf0098470493baf5a48f6c2014357,

title = "A 0.166 pJ/b/pF, 3.5-5 Gb/s TSV I/O Interface with VOHDrift Control",

abstract = "A voltage-mode transmitter (TX) with a predriver and a receiver (RX) with an energy-efficient level shifter (LS) is proposed to reduce power consumption in the heavy load of a through-silicon via (TSV) input-output (I/O) interface. An N-over-N (NN) driver with the proposed predriver reduces VOH drift to enhance jitter characteristics. In addition, the swing level of the transmitted signal can be lowered to 600 mV with a single supply voltage at the TX. To recover the swing level, the RX is designed with the proposed LS that can operate with a data rate of 5 Gb/s. An 8-stacked TSV is emulated in the 65 nm CMOS process, and the emulated capacitance of each stack is 100 fF. The energy efficiency is 0.166 pJ/b/pF with a pseudorandom binary sequence (PRBS)-7 at 5 Gb/s and 0.205 pJ/b/pF with a PRBS-31 at 3.5 Gb/s.",

keywords = "High-bandwidth memory (HBM) interface, Vdrift control, level shifter, low-power input output (I/O), low-swing I/O, on-chip interconnect, single-ended I/O, through-silicon via (TSV)",

author = "Kim, {Ji Young} and Jongsoo Lee and Kiryong Kim and Moon, {Byoung Mo} and Jung, {Seong Ook}",

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AU - Moon, Byoung Mo

AU - Jung, Seong Ook

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N2 - A voltage-mode transmitter (TX) with a predriver and a receiver (RX) with an energy-efficient level shifter (LS) is proposed to reduce power consumption in the heavy load of a through-silicon via (TSV) input-output (I/O) interface. An N-over-N (NN) driver with the proposed predriver reduces VOH drift to enhance jitter characteristics. In addition, the swing level of the transmitted signal can be lowered to 600 mV with a single supply voltage at the TX. To recover the swing level, the RX is designed with the proposed LS that can operate with a data rate of 5 Gb/s. An 8-stacked TSV is emulated in the 65 nm CMOS process, and the emulated capacitance of each stack is 100 fF. The energy efficiency is 0.166 pJ/b/pF with a pseudorandom binary sequence (PRBS)-7 at 5 Gb/s and 0.205 pJ/b/pF with a PRBS-31 at 3.5 Gb/s.

AB - A voltage-mode transmitter (TX) with a predriver and a receiver (RX) with an energy-efficient level shifter (LS) is proposed to reduce power consumption in the heavy load of a through-silicon via (TSV) input-output (I/O) interface. An N-over-N (NN) driver with the proposed predriver reduces VOH drift to enhance jitter characteristics. In addition, the swing level of the transmitted signal can be lowered to 600 mV with a single supply voltage at the TX. To recover the swing level, the RX is designed with the proposed LS that can operate with a data rate of 5 Gb/s. An 8-stacked TSV is emulated in the 65 nm CMOS process, and the emulated capacitance of each stack is 100 fF. The energy efficiency is 0.166 pJ/b/pF with a pseudorandom binary sequence (PRBS)-7 at 5 Gb/s and 0.205 pJ/b/pF with a PRBS-31 at 3.5 Gb/s.

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KW - single-ended I/O

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