A 0.008-mm2, 35-μW, 8.87-ps-resolution CMOS time-to-digital converter using dual-slope architecture

Yeomyung Kim, Doohyun Shon, Tae Wook Kim

Research output: Contribution to journalArticlepeer-review

3 Citations (Scopus)


This paper presents a high resolution time-to-digital converter (TDC) for low-area applications. To achieve both high resolution and low circuit area, we propose a dual-slope voltage-domain TDC, which is composed of a time-to-voltage converter (TVC) and an analog-to-digital converter (ADC). In the TVC, a current source and a capacitor are used to make the circuit as simple as possible. For the same reason, a single-slope ADC, which is commonly used for compact area ADC applications, is adapted and optimized. Because the main non-linearity occurs in the current source of the TVC and the ramp generator of the ADC, a double gain-boosting current source is applied to overcome the low output impedance of the current source in the sub-100-nm CMOS process. The prototype TDC is implemented using a 65-nm CMOS process, and occupies only 0.008 mm2. The measurement result shows a dynamic range with an 8-bit 8.86-ps resolution and an integrated non-linearity of ±1.25 LSB.

Original languageEnglish
Pages (from-to)466-482
Number of pages17
JournalInternational Journal of Circuit Theory and Applications
Issue number4
Publication statusPublished - 2017 Apr 1

Bibliographical note

Publisher Copyright:
Copyright © 2016 John Wiley & Sons, Ltd.

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Computer Science Applications
  • Electrical and Electronic Engineering
  • Applied Mathematics


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