Abstract
The ever-expanding demand for ultra-high-speed interconnects has driven the development of wireline TXs operating at >100Gb/s per lane [1]-[4]. This paper presents a PAM-4 TX achieving 200Gb/s with improved output bandwidth and output swing by minimizing the driver capacitance with pull-up current sources, multiplexing with flexible clock timing control, and employing a fully reconfigurable 5-tap FFE architecture.
Original language | English |
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Title of host publication | 2021 IEEE International Solid-State Circuits Conference, ISSCC 2021 - Digest of Technical Papers |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 128-130 |
Number of pages | 3 |
ISBN (Electronic) | 9781728195490 |
DOIs | |
Publication status | Published - 2021 Feb 13 |
Event | 2021 IEEE International Solid-State Circuits Conference, ISSCC 2021 - San Francisco, United States Duration: 2021 Feb 13 → 2021 Feb 22 |
Publication series
Name | Digest of Technical Papers - IEEE International Solid-State Circuits Conference |
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Volume | 64 |
ISSN (Print) | 0193-6530 |
Conference
Conference | 2021 IEEE International Solid-State Circuits Conference, ISSCC 2021 |
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Country/Territory | United States |
City | San Francisco |
Period | 21/2/13 → 21/2/22 |
Bibliographical note
Publisher Copyright:© 2021 IEEE.
All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering