TY - GEN
T1 - 3D network-on-chip with wireless links through inductive coupling
AU - Lee, Jinho
AU - Zhu, Mingyang
AU - Choi, Kiyoung
AU - Ahn, Jung Ho
AU - Sharma, Rohit
PY - 2011
Y1 - 2011
N2 - Utilizing network-on-chips for manycore SoCs has already been studied widely, as traditional bus-based architectures are unlikely to endure so many inter-core communications. Since device scaling has come to a limit, the technology trend now is stacking dies three-dimensionally to obtain more silicon area and shorter wire length. The most challenging part for making a 3D chip is inter-layer communication method. Currently, TSV is the most popular and promising technique to provide the best performance. However, it suffers from many problems due to inter-layer wiring. As a substitute, inductive coupling can be used as a reliable and non-expensive technology. In this work, we use inductive coupling for the inter-layer communication to build a 3D NoC. We also propose a token bus protocol for an efficient implementation of multi-layer communications. Experimental results show that the proposed architecture achieves maximum throughput of 4.7 flits/cycle under uniform random traffic.
AB - Utilizing network-on-chips for manycore SoCs has already been studied widely, as traditional bus-based architectures are unlikely to endure so many inter-core communications. Since device scaling has come to a limit, the technology trend now is stacking dies three-dimensionally to obtain more silicon area and shorter wire length. The most challenging part for making a 3D chip is inter-layer communication method. Currently, TSV is the most popular and promising technique to provide the best performance. However, it suffers from many problems due to inter-layer wiring. As a substitute, inductive coupling can be used as a reliable and non-expensive technology. In this work, we use inductive coupling for the inter-layer communication to build a 3D NoC. We also propose a token bus protocol for an efficient implementation of multi-layer communications. Experimental results show that the proposed architecture achieves maximum throughput of 4.7 flits/cycle under uniform random traffic.
UR - http://www.scopus.com/inward/record.url?scp=84863160858&partnerID=8YFLogxK
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U2 - 10.1109/isocc.2011.6138783
DO - 10.1109/isocc.2011.6138783
M3 - Conference contribution
AN - SCOPUS:84863160858
SN - 9781457707100
T3 - 2011 International SoC Design Conference, ISOCC 2011
SP - 353
EP - 356
BT - 2011 International SoC Design Conference, ISOCC 2011
PB - IEEE Computer Society
T2 - 8th International SoC Design Conference 2011, ISOCC 2011
Y2 - 17 November 2011 through 18 November 2011
ER -