2.5-V, 333-Mb/s/pin, 1-Gbit, double-data-rate synchronous DRAM

Hongil Yoon; Gi Won Cha; Changsik Yoo; Nam Jong Kim; Keum Yong Kim; Chang Ho Lee; Kyu Nam Lim; Kyuchan Lee; Jun Young Jeon; Tae Sung Jung; Hongsik Jeong; Tae Young Chung; Kinam Kim; Soo In Cho

doi:10.1109/4.799867

2.5-V, 333-Mb/s/pin, 1-Gbit, double-data-rate synchronous DRAM

Hongil Yoon, Gi Won Cha, Changsik Yoo, Nam Jong Kim, Keum Yong Kim, Chang Ho Lee, Kyu Nam Lim, Kyuchan Lee, Jun Young Jeon, Tae Sung Jung, Hongsik Jeong, Tae Young Chung, Kinam Kim, Soo In Cho

Department of Electrical and Electronic Engineering

Research output: Contribution to journal › Article › peer-review

22 Citations (Scopus)

Abstract

A double data rate (DDR) at 333 Mb/s/pin is achieved for a 2.5-V, 1-Gb synchronous DRAM in a 0.14-μm process. The large density of integration and severe device fluctuation present challenges in dealing with the on-chip skews, packaging, and processing technology. Circuit techniques and schemes of outer DQ and inner control (ODIC) chip with non-ODIC package, cycle-time-adaptive wave pipelining, and variable-stage analog delay-locked loop with the three-input phase detector can provide precise skew controls and increased tolerance to processing variations. DDR as a viable high-speed and low-voltage DRAM I/O interface is demonstrated.

Original language	English
Pages (from-to)	1589-1599
Number of pages	11
Journal	IEEE Journal of Solid-State Circuits
Volume	34
Issue number	11
DOIs	https://doi.org/10.1109/4.799867
Publication status	Published - 1999 Nov

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

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10.1109/4.799867

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@article{4bd7f3827eef4d84af245a685b8b6612,

title = "2.5-V, 333-Mb/s/pin, 1-Gbit, double-data-rate synchronous DRAM",

abstract = "A double data rate (DDR) at 333 Mb/s/pin is achieved for a 2.5-V, 1-Gb synchronous DRAM in a 0.14-μm process. The large density of integration and severe device fluctuation present challenges in dealing with the on-chip skews, packaging, and processing technology. Circuit techniques and schemes of outer DQ and inner control (ODIC) chip with non-ODIC package, cycle-time-adaptive wave pipelining, and variable-stage analog delay-locked loop with the three-input phase detector can provide precise skew controls and increased tolerance to processing variations. DDR as a viable high-speed and low-voltage DRAM I/O interface is demonstrated.",

author = "Hongil Yoon and Cha, {Gi Won} and Changsik Yoo and Kim, {Nam Jong} and Kim, {Keum Yong} and Lee, {Chang Ho} and Lim, {Kyu Nam} and Kyuchan Lee and Jeon, {Jun Young} and Jung, {Tae Sung} and Hongsik Jeong and Chung, {Tae Young} and Kinam Kim and Cho, {Soo In}",

year = "1999",

month = nov,

doi = "10.1109/4.799867",

language = "English",

volume = "34",

pages = "1589--1599",

journal = "IEEE Journal of Solid-State Circuits",

issn = "0018-9200",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "11",

}

TY - JOUR

T1 - 2.5-V, 333-Mb/s/pin, 1-Gbit, double-data-rate synchronous DRAM

AU - Yoon, Hongil

AU - Cha, Gi Won

AU - Yoo, Changsik

AU - Kim, Nam Jong

AU - Kim, Keum Yong

AU - Lee, Chang Ho

AU - Lim, Kyu Nam

AU - Lee, Kyuchan

AU - Jeon, Jun Young

AU - Jung, Tae Sung

AU - Jeong, Hongsik

AU - Chung, Tae Young

AU - Kim, Kinam

AU - Cho, Soo In

PY - 1999/11

Y1 - 1999/11

N2 - A double data rate (DDR) at 333 Mb/s/pin is achieved for a 2.5-V, 1-Gb synchronous DRAM in a 0.14-μm process. The large density of integration and severe device fluctuation present challenges in dealing with the on-chip skews, packaging, and processing technology. Circuit techniques and schemes of outer DQ and inner control (ODIC) chip with non-ODIC package, cycle-time-adaptive wave pipelining, and variable-stage analog delay-locked loop with the three-input phase detector can provide precise skew controls and increased tolerance to processing variations. DDR as a viable high-speed and low-voltage DRAM I/O interface is demonstrated.

AB - A double data rate (DDR) at 333 Mb/s/pin is achieved for a 2.5-V, 1-Gb synchronous DRAM in a 0.14-μm process. The large density of integration and severe device fluctuation present challenges in dealing with the on-chip skews, packaging, and processing technology. Circuit techniques and schemes of outer DQ and inner control (ODIC) chip with non-ODIC package, cycle-time-adaptive wave pipelining, and variable-stage analog delay-locked loop with the three-input phase detector can provide precise skew controls and increased tolerance to processing variations. DDR as a viable high-speed and low-voltage DRAM I/O interface is demonstrated.

UR - http://www.scopus.com/inward/record.url?scp=0033221599&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0033221599&partnerID=8YFLogxK

U2 - 10.1109/4.799867

DO - 10.1109/4.799867

M3 - Article

AN - SCOPUS:0033221599

SN - 0018-9200

VL - 34

SP - 1589

EP - 1599

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

IS - 11

ER -

2.5-V, 333-Mb/s/pin, 1-Gbit, double-data-rate synchronous DRAM

Abstract

All Science Journal Classification (ASJC) codes

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