25-Gb/s Clocked Pluggable Optics for High-Density Data Center Interconnections

Gyu Seob Jeong, Jeongho Hwang, Hong Seok Choi, Hyungrok Do, Daehyun Koh, Daeyoung Yun, Jinhyung Lee, Kwanseo Park, Han Gon Ko, Kwangho Lee, Jiho Joo, Gyungock Kim, Deog Kyoon Jeong

Research output: Contribution to journalArticlepeer-review

2 Citations (Scopus)


This brief presents a clocked pluggable optics suitable for high-density data center interconnections. The proposed architecture performs a SERDES function at the module side by exploiting a forwarded clock from the ASIC. Due to the relaxed channel loss of the ASIC-to-module interface, the use of power-hungry equalizers can be avoided. Based on an 850-nm multi-mode fiber interface, a 25-Gb/s link operation is demonstrated. A vertical-cavity surface-emitting laser-based transmitter outputs an optical modulation power of 0.6 mW. The optical receiver sensitivity is measured to be-7.5 dBm at 21.2 Gb/s with an optical excitation, and 120 μ App at 25 Gb/s with an electrical excitation. The jitter tracking capability of the implemented clock and data recovery is evaluated in the presence of ±100-ppm frequency offsets and the measured jitter tolerance complies with the 100 GbE specification well. The optical transceiver is implemented in 65-nm CMOS technology and consumes 281 mW at 25 Gb/s, corresponding to the energy efficiency of 11.2 pJ/b.

Original languageEnglish
Article number8395366
Pages (from-to)1395-1399
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Issue number10
Publication statusPublished - 2018 Oct

Bibliographical note

Publisher Copyright:
© 2004-2012 IEEE.

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering


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