2-Level LFSR scheme with asynchronous test pattern transfer for low cost and high efficiency built-in-self-test

S. M. Yoo; S. O. Jung; S. M. Kang

2-Level LFSR scheme with asynchronous test pattern transfer for low cost and high efficiency built-in-self-test

S. M. Yoo, S. O. Jung, S. M. Kang

Department of Electrical and Electronic Engineering

Research output: Contribution to journal › Conference article › peer-review

1 Citation (Scopus)

Abstract

This paper describes a new test pattern generator to increase fault coverage and a test pattern transferring method to reduce test time without large hardware overhead in the BIST structure. The new pattern generator uses a 2-level LFSR scheme in which inputs are varied and controlled by the counter output. An asynchronous internal clock generated by an internal ring-oscillator is used for fast test pattern transfer into the scan chain. The new 2-level LFSR scheme is verified by the HITEC fault simulator.

Original language	English
Pages (from-to)	93-96
Number of pages	4
Journal	Proceedings of the IEEE Great Lakes Symposium on VLSI
Publication status	Published - 2001
Event	11th Great Lakes Sysmposium on VLSI (GLSVLSI 2001) - West Lafayette, IN, United States Duration: 2001 Mar 22 → 2001 Mar 23

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Cite this

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title = "2-Level LFSR scheme with asynchronous test pattern transfer for low cost and high efficiency built-in-self-test",

abstract = "This paper describes a new test pattern generator to increase fault coverage and a test pattern transferring method to reduce test time without large hardware overhead in the BIST structure. The new pattern generator uses a 2-level LFSR scheme in which inputs are varied and controlled by the counter output. An asynchronous internal clock generated by an internal ring-oscillator is used for fast test pattern transfer into the scan chain. The new 2-level LFSR scheme is verified by the HITEC fault simulator.",

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year = "2001",

language = "English",

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journal = "Proceedings of the IEEE Great Lakes Symposium on VLSI",

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note = "11th Great Lakes Sysmposium on VLSI (GLSVLSI 2001) ; Conference date: 22-03-2001 Through 23-03-2001",

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AU - Yoo, S. M.

AU - Jung, S. O.

AU - Kang, S. M.

PY - 2001

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N2 - This paper describes a new test pattern generator to increase fault coverage and a test pattern transferring method to reduce test time without large hardware overhead in the BIST structure. The new pattern generator uses a 2-level LFSR scheme in which inputs are varied and controlled by the counter output. An asynchronous internal clock generated by an internal ring-oscillator is used for fast test pattern transfer into the scan chain. The new 2-level LFSR scheme is verified by the HITEC fault simulator.

AB - This paper describes a new test pattern generator to increase fault coverage and a test pattern transferring method to reduce test time without large hardware overhead in the BIST structure. The new pattern generator uses a 2-level LFSR scheme in which inputs are varied and controlled by the counter output. An asynchronous internal clock generated by an internal ring-oscillator is used for fast test pattern transfer into the scan chain. The new 2-level LFSR scheme is verified by the HITEC fault simulator.

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M3 - Conference article

AN - SCOPUS:0034996831

SN - 1066-1395

SP - 93

EP - 96

JO - Proceedings of the IEEE Great Lakes Symposium on VLSI

JF - Proceedings of the IEEE Great Lakes Symposium on VLSI

T2 - 11th Great Lakes Sysmposium on VLSI (GLSVLSI 2001)

Y2 - 22 March 2001 through 23 March 2001

ER -

2-Level LFSR scheme with asynchronous test pattern transfer for low cost and high efficiency built-in-self-test

Abstract

All Science Journal Classification (ASJC) codes

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