2-D Failure Bitmap Compression Using Line Fault Marking Method

Keewon Cho; Young Woo Lee; Sungyoul Seo; Sungho Kang

doi:10.1109/ISOCC.2018.8649886

2-D Failure Bitmap Compression Using Line Fault Marking Method

Keewon Cho, Young Woo Lee, Sungyoul Seo, Sungho Kang

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

As memory densities have rapidly increased, memory testing and repairing processes are the major keys to prevent the decline in the yield. For redundancy analysis (RA), fail addresses should be extracted by the external automatic test equipment (ATE) and stored into the failure bitmap. However, full size of the failure bitmap can be a huge burden on the ATE costs. In order to reduce the storage size, this paper presents a new failure bitmap compression method. The proposed method marks all of the addresses of the line fault, so that repairing solutions can be easily decided. Experimental results show that the proposed compression method greatly reduces the size of failure bitmap while minimizing the failure data loss.

Original language	English
Title of host publication	Proceedings - International SoC Design Conference 2018, ISOCC 2018
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	21-22
Number of pages	2
ISBN (Electronic)	9781538679609
DOIs	https://doi.org/10.1109/ISOCC.2018.8649886
Publication status	Published - 2019 Feb 22
Event	15th International SoC Design Conference, ISOCC 2018 - Daegu, Korea, Republic of Duration: 2018 Nov 12 → 2018 Nov 15

Publication series

Name	Proceedings - International SoC Design Conference 2018, ISOCC 2018

Conference

Conference	15th International SoC Design Conference, ISOCC 2018
Country/Territory	Korea, Republic of
City	Daegu
Period	18/11/12 → 18/11/15

Bibliographical note

Funding Information:
This research was supported by the MOTIE(Ministry of Trade, Industry & Energy(10067813) and KSRC(Korea Semiconductor Research Consortium) support program for the development of the future semiconductor device.

Funding Information:
ACKNOWLEDGMENT This research was supported by the MOTIE(Ministry of Trade, Industry & Energy(10067813) and KSRC(Korea Semiconductor Research Consortium) support program for the development of the future semiconductor device.

Publisher Copyright:
© 2018 IEEE.

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering
Electronic, Optical and Magnetic Materials

Access to Document

10.1109/ISOCC.2018.8649886

Cite this

Cho, K., Lee, Y. W., Seo, S., & Kang, S. (2019). 2-D Failure Bitmap Compression Using Line Fault Marking Method. In Proceedings - International SoC Design Conference 2018, ISOCC 2018 (pp. 21-22). Article 8649886 (Proceedings - International SoC Design Conference 2018, ISOCC 2018). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC.2018.8649886

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abstract = "As memory densities have rapidly increased, memory testing and repairing processes are the major keys to prevent the decline in the yield. For redundancy analysis (RA), fail addresses should be extracted by the external automatic test equipment (ATE) and stored into the failure bitmap. However, full size of the failure bitmap can be a huge burden on the ATE costs. In order to reduce the storage size, this paper presents a new failure bitmap compression method. The proposed method marks all of the addresses of the line fault, so that repairing solutions can be easily decided. Experimental results show that the proposed compression method greatly reduces the size of failure bitmap while minimizing the failure data loss.",

author = "Keewon Cho and Lee, {Young Woo} and Sungyoul Seo and Sungho Kang",

note = "Funding Information: This research was supported by the MOTIE(Ministry of Trade, Industry & Energy(10067813) and KSRC(Korea Semiconductor Research Consortium) support program for the development of the future semiconductor device. Funding Information: ACKNOWLEDGMENT This research was supported by the MOTIE(Ministry of Trade, Industry & Energy(10067813) and KSRC(Korea Semiconductor Research Consortium) support program for the development of the future semiconductor device. Publisher Copyright: {\textcopyright} 2018 IEEE.; 15th International SoC Design Conference, ISOCC 2018 ; Conference date: 12-11-2018 Through 15-11-2018",

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language = "English",

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Cho, K, Lee, YW, Seo, S & Kang, S 2019, 2-D Failure Bitmap Compression Using Line Fault Marking Method. in Proceedings - International SoC Design Conference 2018, ISOCC 2018., 8649886, Proceedings - International SoC Design Conference 2018, ISOCC 2018, Institute of Electrical and Electronics Engineers Inc., pp. 21-22, 15th International SoC Design Conference, ISOCC 2018, Daegu, Korea, Republic of, 18/11/12. https://doi.org/10.1109/ISOCC.2018.8649886

2-D Failure Bitmap Compression Using Line Fault Marking Method. / Cho, Keewon; Lee, Young Woo; Seo, Sungyoul et al.
Proceedings - International SoC Design Conference 2018, ISOCC 2018. Institute of Electrical and Electronics Engineers Inc., 2019. p. 21-22 8649886 (Proceedings - International SoC Design Conference 2018, ISOCC 2018).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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N1 - Funding Information: This research was supported by the MOTIE(Ministry of Trade, Industry & Energy(10067813) and KSRC(Korea Semiconductor Research Consortium) support program for the development of the future semiconductor device. Funding Information: ACKNOWLEDGMENT This research was supported by the MOTIE(Ministry of Trade, Industry & Energy(10067813) and KSRC(Korea Semiconductor Research Consortium) support program for the development of the future semiconductor device. Publisher Copyright: © 2018 IEEE.

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AB - As memory densities have rapidly increased, memory testing and repairing processes are the major keys to prevent the decline in the yield. For redundancy analysis (RA), fail addresses should be extracted by the external automatic test equipment (ATE) and stored into the failure bitmap. However, full size of the failure bitmap can be a huge burden on the ATE costs. In order to reduce the storage size, this paper presents a new failure bitmap compression method. The proposed method marks all of the addresses of the line fault, so that repairing solutions can be easily decided. Experimental results show that the proposed compression method greatly reduces the size of failure bitmap while minimizing the failure data loss.

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2-D Failure Bitmap Compression Using Line Fault Marking Method

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