1.25/2.5-Gb/s Dual Bit-Rate Burst-Mode Clock Recovery Circuits in 0.18-μm CMOS Technology

Pyung Su Han; Woo Young Choi

doi:10.1109/TCSII.2006.884120

1.25/2.5-Gb/s Dual Bit-Rate Burst-Mode Clock Recovery Circuits in 0.18-μm CMOS Technology

Pyung Su Han, Woo Young Choi

Department of Electrical and Electronic Engineering

Research output: Contribution to journal › Article › peer-review

18 Citations (Scopus)

Abstract

A burst-mode clock recovery circuit with a novel dual bit-rate structure is presented. It utilizes two gated oscillators to align the clock with data edges and can operate in half-rate clocking mode, doubling data throughput, as well as in full-rate clocking mode. The gated oscillator reset-phase control scheme causes the starting phase of gated oscillators to alternate repeatedly between 0° and 180° according to the current clock phase. A prototype chip was designed with the 0.18-μm CMOS technology, and a 1.25/2.5-Gb/s dual-mode operation was verified by measurement.

Original language	English
Pages (from-to)	38-42
Number of pages	5
Journal	IEEE Transactions on Circuits and Systems II: Express Briefs
Volume	54
Issue number	1
DOIs	https://doi.org/10.1109/TCSII.2006.884120
Publication status	Published - 2007 Jan

Bibliographical note

Funding Information:
Manuscript received October 9, 2005; revised May 18, 2006. This work was supported by the Ministry of Science and Technology of Korea and the Ministry of Commerce, Industry and Energy through the System IC 2010 program. This paper was recommended by Associate Editor J. Liu.

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

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10.1109/TCSII.2006.884120

Cite this

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abstract = "A burst-mode clock recovery circuit with a novel dual bit-rate structure is presented. It utilizes two gated oscillators to align the clock with data edges and can operate in half-rate clocking mode, doubling data throughput, as well as in full-rate clocking mode. The gated oscillator reset-phase control scheme causes the starting phase of gated oscillators to alternate repeatedly between 0° and 180° according to the current clock phase. A prototype chip was designed with the 0.18-μm CMOS technology, and a 1.25/2.5-Gb/s dual-mode operation was verified by measurement.",

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note = "Funding Information: Manuscript received October 9, 2005; revised May 18, 2006. This work was supported by the Ministry of Science and Technology of Korea and the Ministry of Commerce, Industry and Energy through the System IC 2010 program. This paper was recommended by Associate Editor J. Liu.",

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AB - A burst-mode clock recovery circuit with a novel dual bit-rate structure is presented. It utilizes two gated oscillators to align the clock with data edges and can operate in half-rate clocking mode, doubling data throughput, as well as in full-rate clocking mode. The gated oscillator reset-phase control scheme causes the starting phase of gated oscillators to alternate repeatedly between 0° and 180° according to the current clock phase. A prototype chip was designed with the 0.18-μm CMOS technology, and a 1.25/2.5-Gb/s dual-mode operation was verified by measurement.

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1.25/2.5-Gb/s Dual Bit-Rate Burst-Mode Clock Recovery Circuits in 0.18-μm CMOS Technology

Abstract

Bibliographical note

All Science Journal Classification (ASJC) codes

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