1 Gbit SDRAM with an independent sub-array controlled scheme and a hierarchical decoding scheme

K. C. Lee; H. Yoon; S. B. Lee; J. H. Lee; B. S. Moon; K. Y. Kim; C. H. Kim; S. I. Cho

1 Gbit SDRAM with an independent sub-array controlled scheme and a hierarchical decoding scheme

K. C. Lee, H. Yoon, S. B. Lee, J. H. Lee, B. S. Moon, K. Y. Kim, C. H. Kim, S. I. Cho

Department of Electrical and Electronic Engineering

Research output: Contribution to conference › Paper › peer-review

5 Citations (Scopus)

Abstract

A prototype 1 Gbit synchronous dynamic random access memory (SDRAM) with independent array controlled isolation and decoding schemes is demonstrated. A fully working device with a size of 570 mm² is fabricated using a 0.16 μm CMOS process. The design techniques utilizing the independent sub-array controlled scheme and the hierarchical decoding scheme to achieve enhanced failure analysis, lower power consumption, and smaller chip size, are presented.

Original language	English
Pages	103-104
Number of pages	2
Publication status	Published - 1997
Event	Proceedings of the 1997 Symposium on VLSI Circuits - Kyoto, Jpn Duration: 1997 Jun 12 → 1997 Jun 14

Other

Other	Proceedings of the 1997 Symposium on VLSI Circuits
City	Kyoto, Jpn
Period	97/6/12 → 97/6/14

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Cite this

@conference{d02c59633b9940c4bec9924586019af2,

title = "1 Gbit SDRAM with an independent sub-array controlled scheme and a hierarchical decoding scheme",

abstract = "A prototype 1 Gbit synchronous dynamic random access memory (SDRAM) with independent array controlled isolation and decoding schemes is demonstrated. A fully working device with a size of 570 mm2 is fabricated using a 0.16 μm CMOS process. The design techniques utilizing the independent sub-array controlled scheme and the hierarchical decoding scheme to achieve enhanced failure analysis, lower power consumption, and smaller chip size, are presented.",

author = "Lee, {K. C.} and H. Yoon and Lee, {S. B.} and Lee, {J. H.} and Moon, {B. S.} and Kim, {K. Y.} and Kim, {C. H.} and Cho, {S. I.}",

year = "1997",

language = "English",

pages = "103--104",

note = "Proceedings of the 1997 Symposium on VLSI Circuits ; Conference date: 12-06-1997 Through 14-06-1997",

}

TY - CONF

T1 - 1 Gbit SDRAM with an independent sub-array controlled scheme and a hierarchical decoding scheme

AU - Lee, K. C.

AU - Yoon, H.

AU - Lee, S. B.

AU - Lee, J. H.

AU - Moon, B. S.

AU - Kim, K. Y.

AU - Kim, C. H.

AU - Cho, S. I.

PY - 1997

Y1 - 1997

N2 - A prototype 1 Gbit synchronous dynamic random access memory (SDRAM) with independent array controlled isolation and decoding schemes is demonstrated. A fully working device with a size of 570 mm2 is fabricated using a 0.16 μm CMOS process. The design techniques utilizing the independent sub-array controlled scheme and the hierarchical decoding scheme to achieve enhanced failure analysis, lower power consumption, and smaller chip size, are presented.

AB - A prototype 1 Gbit synchronous dynamic random access memory (SDRAM) with independent array controlled isolation and decoding schemes is demonstrated. A fully working device with a size of 570 mm2 is fabricated using a 0.16 μm CMOS process. The design techniques utilizing the independent sub-array controlled scheme and the hierarchical decoding scheme to achieve enhanced failure analysis, lower power consumption, and smaller chip size, are presented.

UR - http://www.scopus.com/inward/record.url?scp=0031374804&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0031374804&partnerID=8YFLogxK

M3 - Paper

AN - SCOPUS:0031374804

SP - 103

EP - 104

T2 - Proceedings of the 1997 Symposium on VLSI Circuits

Y2 - 12 June 1997 through 14 June 1997

ER -

1 Gbit SDRAM with an independent sub-array controlled scheme and a hierarchical decoding scheme

Abstract

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All Science Journal Classification (ASJC) codes

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