Calculated based on number of publications stored in Pure and citations from Scopus
20002024

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  • 2013

    Comparative analysis of 1:1:2 and 1:2:2 FinFET SRAM bit-cell using assist circuit

    Kang, K., Jeong, H., Lee, J. & Jung, S. O., 2013, ISOCC 2013 - 2013 International SoC Design Conference. IEEE Computer Society, p. 35-38 4 p. 6863979. (ISOCC 2013 - 2013 International SoC Design Conference).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    2 Citations (Scopus)
  • Comparative study for SRAM cells in near and sub-threshold region

    Yang, Y. H., Park, J. H., Song, S. C., Yang, F., Wang, J., Yeap, G. & Jung, S. O., 2013, China Semiconductor Technology International Conference 2013, CSTIC 2013. 1 ed. p. 93-98 6 p. (ECS Transactions; vol. 52, no. 1).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • Sensing circuit optimization using different type of transistors for deep submicron STT-RAM

    Song, B., Na, T., Kim, J., Kang, S. H., Kim, J. P. & Jung, S. O., 2013, ISOCC 2013 - 2013 International SoC Design Conference. IEEE Computer Society, p. 68-71 4 p. 6863987. (ISOCC 2013 - 2013 International SoC Design Conference).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • Source follower based single ended sense amplifier for large capacity SRAM

    Jung, D. H., Jeong, H., Song, T., Kim, G. & Jung, S. O., 2013, ISOCC 2013 - 2013 International SoC Design Conference. IEEE Computer Society, p. 364-367 4 p. 6864051. (ISOCC 2013 - 2013 International SoC Design Conference).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    1 Citation (Scopus)
  • 2012

    A low-power and small-area all-digital delay-locked loop with closed-loop duty-cycle correction

    Jung, D. H., Ryu, K., Park, J. H. & Jung, S. O., 2012, 2012 Proceedings of the European Solid State Circuits Conference, ESSCIRC 2012. p. 181-184 4 p. 6341288. (European Solid-State Circuits Conference).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    11 Citations (Scopus)
  • Impact of fin thickness and height on read stability / write ability in tri-gate FinFET based SRAM

    Lee, J., Jeong, H., Yang, Y., Kim, J. & Jung, S. O., 2012, ISOCC 2012 - 2012 International SoC Design Conference. p. 479-482 4 p. 6406900. (ISOCC 2012 - 2012 International SoC Design Conference).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    4 Citations (Scopus)
  • Integration of dual channel timing formatter system for high speed memory test equipment

    Park, J., Lee, I., Park, Y. S., Kim, S. G., Ryu, K. H., Jung, D. H., Jo, K., Lee, C. K., Yoon, H., Jung, S. O., Choi, W. Y. & Kang, S., 2012, ISOCC 2012 - 2012 International SoC Design Conference. p. 185-187 3 p. 6407070. (ISOCC 2012 - 2012 International SoC Design Conference).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    4 Citations (Scopus)
  • Static read stability and write ability metrics in FinFET based SRAM considering read and write-assist circuits

    Jeong, H., Yang, Y., Lee, J., Kim, J. & Jung, S. O., 2012, 2012 19th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2012. p. 833-836 4 p. 6463530. (2012 19th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2012).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    2 Citations (Scopus)
  • 2011

    MTJ based non-volatile flip-flop in deep submicron technology

    Jung, Y., Kim, J., Ryu, K., Jung, S. O., Kim, J. P. & Kang, S. H., 2011, 2011 International SoC Design Conference, ISOCC 2011. IEEE Computer Society, p. 424-427 4 p. (2011 International SoC Design Conference, ISOCC 2011).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    12 Citations (Scopus)
  • SRAM bitcell design for low voltage operation in deep submicron technologies

    Yang, Y. H., Kim, J., Park, H., Wang, J., Yeap, G. & Jung, S. O., 2011, 2011 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2011. 5783219. (2011 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2011).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    3 Citations (Scopus)
  • 2010

    Accurate projection of Vccmin by modeling "dual slope" in FinFET based SRAM, and impact of long term reliability on end of life V ccmin

    Park, H., Song, S. C., Woo, S. H., Abu-Rahma, M. H., Ge, L., Kang, M. G., Han, B. M., Wang, J., Choi, R., Yang, J. W., Jung, S. O. & Yeap, G., 2010, 2010 IEEE International Reliability Physics Symposium, IRPS 2010. p. 1008-1013 6 p. 5488684. (IEEE International Reliability Physics Symposium Proceedings).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    10 Citations (Scopus)
  • Process variation tolerant all-digital multiphase DLL for DDR3 interface

    Kang, H. C., Ryu, K. H., Lee, D. H., Lee, W., Kim, S. H., Choi, J. R. & Jung, S. O., 2010, IEEE Custom Integrated Circuits Conference 2010, CICC 2010. 5617474. (Proceedings of the Custom Integrated Circuits Conference).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    10 Citations (Scopus)
  • 2008

    Statistical modeling of layout-dependent characteristic fluctuations for multi-finger MOSFETs

    Park, C., Kang, J., Jung, S. O. & Yun, I., 2008, 2008 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC. 4760677. (2008 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    3 Citations (Scopus)
  • 2007

    Slope interconnect effort: Gate-interconnect interdependentdelay model for CMOS logic gates

    Hwang, M. E., Jung, S. O. & Roy, K., 2007, ISLPED'07: Proceedings of the 2007 International Symposium on Low Power Electronics and Design. p. 387-390 4 p. (Proceedings of the International Symposium on Low Power Electronics and Design).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    1 Citation (Scopus)
  • 2006

    Thyristor-based volatile memory in nano-scale CMOS

    Roy, R., Nemati, F., Young, K., Bateman, B., Chopra, R., Jung, S. O., Show, C. & Cho, H. J., 2006, 2006 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers. p. 632+621 1696327. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    6 Citations (Scopus)
  • 2002

    Low-swing clock domino logic incorporating dual supply and dual threshold voltages

    Jung, S. O., Kim, K. W. & Kang, S. M., 2002, Proceedings of the 39th Annual Design Automation Conference, DAC'02. Institute of Electrical and Electronics Engineers Inc., p. 467-472 6 p. (Proceedings - Design Automation Conference).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    11 Citations (Scopus)
  • Optimal timing for skew-tolerant high-speed domino logic

    Jung, S. O., Kim, K. W. & Kang, S. M., 2002, Proceedings - IEEE Computer Society Annual Symposium on VLSI: New Paradigms for VLSI Systems Design, ISVLSI 2002. Smailagic, A. & Brodersen, R. (eds.). IEEE Computer Society, p. 41-46 6 p. 1016871. (Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI; vol. 2002-January).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    3 Citations (Scopus)
  • 2001

    Coupling-aware minimum delay optimization for domino logic circuits

    Kim, K. W., Jung, S. O. & Kang, S. M., 2001, ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings. IEEE Computer Society, p. 371-374 4 p. 922062. (ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings; vol. 5).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • Low cost and high efficiency BIST scheme with 2-level LFSR and ATPT

    Yoo, S. M., Jung, S. O. & Kang, S. M., 2001, ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings. p. 1-4 4 p. 922153. (ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings; vol. 4).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    2 Citations (Scopus)
  • New current-mode sense amplifiers for high density DRAM and PIM architectures

    Yoo, S. M., Kim, C., Jung, S. O., Baek, K. H. & Kang, S. M. S., 2001, ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings. p. 938-941 4 p. 922393. (ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings; vol. 4).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    1 Citation (Scopus)
  • Noise constrained power optimization for dual V/sub T/ domino logic

    Jung, S. O., Kim, K. W. & Kang, S. M., 2001, ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings. p. 158-161 4 p. 922196. (ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings; vol. 4).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    1 Citation (Scopus)
  • Skew-tolerant high-speed (STHS) domino logic

    Jung, S. O., Yoo, S. M., Kim, K. W. & Kang, S. M., 2001, ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings. p. 154-157 4 p. 922195. (ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings; vol. 4).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    30 Citations (Scopus)